EMC/EMI & ESD Checklist

This checklist is prepared to ensure early-stage compliance of hardware products with electromagnetic compatibility (EMC), electromagnetic interference (EMI), and electrostatic discharge (ESD) requirements. The goal is to minimize the risk of failure in official tests such as CE/FCC by taking measures during the design phase.

EMC Planning and Standardization​

1. Are the EMC standards applicable to the product defined?​

EMC standards applicable according to product class, usage environment, and market should be determined. Example classifications:

• EN 55032 / CISPR 32: Multimedia, information technology equipment (IT/AV)
• EN 55035 / CISPR 35: Immunity tests
• EN 61000-6-1 / -6-3: Industrial and residential general applications
• EN 61326-1: Laboratory and measurement equipment
• FCC Part 15 Class A/B: US market compliance
• ICES-003: Canada compliance

Applied standards should be listed in "EMC Requirements Matrix" document and limit values for each standard (radiated, conducted, harmonic, flicker) should be documented in technical file.

2. Is EMC test scope and test laboratory selection made?​

Scope of tests to be applied for the product and laboratories to perform them should be selected at early stage.

• Accredited laboratories (ISO/IEC 17025) should be preferred
• Test scope: Radiated Emission (30 MHz–6 GHz), Conducted Emission (150 kHz–30 MHz), ESD Immunity (±8 kV air, ±4 kV contact), EFT/Burst, Surge, Dips, Conducted Immunity, Radiated Immunity
• Pre-scan plan (early prototype tests) should be prepared, critical frequency ranges should be determined
• Test laboratory should share test setup with manufacturer; cable routings, power supply types, and test modes should be defined

3. Is EMC/EMI plan created during design phase?​

EMC/EMI plan to be applied in each design cycle should be prepared and integrated into design verification plan (DVP&R). Plan content:

• Measurement target ranges: 30 MHz–6 GHz, if required 9 kHz lower band (conducted)
• Emission limits: CISPR Class A/B limit values (e.g., 40 dBµV/m @ 3 m)
• Immunity target: 3 V/m (general industrial), 10 V/m (critical systems)
• Design-level targets: 40 dB EMI suppression at power input, line filter and ferrite selections, grounding and shielding plan on PCB (GND stitching, copper pour)

Plan should be tracked in project management system under "EMC Control Plan" title.

4. Is EMC responsible / test engineer assigned to project?​

EMC verification should be conducted by an expert who plays an active role throughout the design process, not just in the test phase.

• EMC responsible or test engineer should be assigned at project start
• This person ensures coordination between electrical, mechanical, and software teams
• Responsibilities: conduct EMC design reviews, analyze pre-scan test results, determine EMI/ESD corrective measures, conduct technical communication with laboratory for final test

This role should be clearly defined in "RACI Matrix" in project documents.

Circuit & Layout Measures​

5. Is grounding strategy defined?​

Grounding structure directly affects system EMI performance.

• Analog, digital, and power grounds should be joined from a single point (star topology)
• GND separation (AGND, DGND, PGND) should be made; junction point is usually selected close to ADC or power input
• In comprehensive systems, low-impedance connection vias should be used between multiple layer grounds
• Chassis ground and signal ground should be connected through RC or ferrite when necessary

6. Are reference planes (ground/power plane) complete in layer structure?​

Ground and power planes in PCB layer structure should be continuous and uninterrupted.

• Holes, cutouts, or via passages on GND plane should be minimized as much as possible
• There should be a continuous reference plane under each high-speed signal line
• Current return should be supported with close ground vias in inter-layer reference transitions (e.g., GND → GND)
• Split-plane regions should not force signal lines to pass through two different reference areas

7. Are high-speed lines (clock, USB, LVDS, RF) impedance controlled?​

All high-speed lines should be routed with impedance-controlled PCB rules.

• 50 Ω ±10% should be targeted for single-ended lines, 90–100 Ω differential for differential lines
• "Impedance coupon" measurements should be performed with PCB manufacturer
• Trace width, layer thickness, and dielectric constant (Dk) should be determined during design
• Microstrip or coplanar waveguide structure should be preferred for RF lines (e.g., antenna feed, PA output)

8. Is return path continuity maintained?​

Return current of each signal should flow to reference plane over the lowest impedance path.

• There should be continuous GND plane under high-speed lines
• Close ground stitching via should be added in case of reference change (e.g., signal passing to different layer via via)
• If return current splits, EMI emission increases and signal integrity degrades

9. Is ground via proximity checked in inter-layer transition (via)?​

When a signal passes from one layer to another via via, current return should be provided at the same point.

• At least one ground stitching via should be placed at 3 mm or closer distance for each signal via
• This distance should be reduced to 1–1.5 mm in RF or differential lines
• This practice reduces EMI, maintains impedance continuity, and reduces cross-talk

This principle is a critical design rule in Howard Johnson – High-Speed Signal Integrity Rule Set.

10. Is multi-layer capacitor placement optimized for power-plane decoupling?​

Multi-decoupling capacitor network should be applied to reduce high-frequency noise between power and ground planes:

• 0.1 µF (high frequency) + 1 µF (medium) + 10 µF (low frequency) combination
• Should be placed as close as possible to power pin of each IC
• Capacitor–via length should be shorter than 5 mm
• MLCC + tantalum combination can be used for different frequency responses in multilayer boards

This approach is based on Target Impedance below 100 mΩ (20 MHz–100 MHz) rule.

11. Are ferrite beads / LC filters positioned at inputs and outputs?​

Appropriate ferrite/LC filter should be placed on each power input or external connection line:

• Input: AC/DC adapter line, USB, Ethernet, motor driver supply
• Output: RF module, sensor, analog measurement circuit
• Ferrite bead attenuates EMI energy without cutting signal (e.g., 100–600 Ω @100 MHz)
• Ferrite selection should be made according to frequency response and current capacity

12. Is clock trace length and routing designed to produce minimum EMI?​

Clock lines are the most critical sources in terms of EMI.

• Trace length should be kept minimum and if necessary surrounded by shield ground lines
• Clock sources (crystal, oscillator) should be positioned away from power circuits
• Clock buffers should be selected with low rise-time drivers (slew-rate controlled)
• There should be no interruption under clock lines in layer transitions
• Local ground ring (guard ring) should be used around PLL and MCU

13. Is loop area minimized around high-current paths (MOSFET drain, motor drivers)?​

Loop area in high-current carrying lines (e.g., motor phase, MOSFET drain) is the main cause of EMI sources.

• Current return path should be provided at shortest distance
• MOSFET, driver, and shunt resistor should be placed with compact "current cell" topology
• These lines should be close to low-impedance ground
• If necessary, these areas should be shielded with ground copper pour or "shield island"

14. Are reset, GPIO, and external I/O lines protected with RC filter or ferrite against EMI ingress?​

Low-speed signals in external interfaces are open to EMI ingress.

• 10–100 Ω series resistor or 100 pF RC filter should be added to lines such as reset, enable, GPIO, ADC inputs
• TVS diodes or ferrite beads should be used for ESD protection
• Common-mode choke is recommended for EMI suppression in external sensor cables

Cabling and Connection Measures​

15. Is use of shielded cable evaluated for external cables?​

Shielded type selection should be evaluated for external cable connections (e.g., power, communication, sensor, motor cables).

• Full shield (foil + braid) is recommended for high-speed lines such as RF, Ethernet, USB, RS-485
• Magnetic shielded (braid + ferrite) structures should be preferred for power cables to reduce EMI emission
• Unshielded cables should only be used in low-frequency, short-distance (less than 30 cm) applications
• Shield resistance should be 10 mΩ/10 cm or lower, continuity tests should be performed after production

16. Is cable shield (braid/foil) grounded from correct point (single-end or 360° clamp)?​

Cable shield grounding point should be selected according to system topology:

• Single-end grounding: Low-frequency, analog lines (e.g., sensor, reference signal)
• Both-end grounding: High-frequency digital lines (e.g., USB, Ethernet, RF)
• 360° connection: Direct contact to chassis surface should be provided with metal clamp or EMC gland
• Surface resistance should be 2.5 mΩ or lower for screw ground connections, paint or oxide layer should be cleaned

Incorrect connection (only wire end, low contact area) seriously reduces EMI suppression effectiveness.

17. Are ferrite bead or common-mode choke added at cable input-outputs?​

Common-mode noise suppressor elements should be used at cable input/output points:

• Ferrite beads (e.g., 100–600 Ω @100 MHz) can be wound or pass-through type on cable
• Common-mode choke should be preferred for multiple lines (Ethernet, CAN, USB)
• Ferrite material selection should be made according to application location: NiZn: 10–100 MHz (digital lines), MnZn: 100 kHz–10 MHz (power lines)
• Impedance change of ferrites under temperature and DC bias should be considered

18. Does connector metal shell connect to chassis with 360° contact?​

Connector shell (e.g., D-Sub, USB, RJ45, M12) should be mounted mechanically to provide 360° electrical contact to chassis.

• Metal shell should be connected to chassis ground with lowest impedance
• Spring EMC gaskets (finger gasket) or metal shield washers can be used for connection
• Metal coating (conductive coating) can be applied around connector in plastic enclosures
• Surface conductivity of connection points should be tested periodically (lower than 2 mΩ)

19. Are EMI/ESD protection elements (TVS, RC filter) defined in external ports?​

All user-accessible ports should be protected against EMI and ESD:

• TVS diodes: should withstand ±8 kV (contact), ±15 kV (air)
• RC filters: typical combination of 100 Ω / 100 pF, should be optimized in high-impedance lines
• Low-capacitance ESD protection (C less than 1 pF) should be preferred in Ethernet / USB lines
• GDT or MOV additional protection elements should be used for high-energy lines (24 V, 48 V)

20. Are cable length and routing determined appropriately for test conditions?​

Cabling layout should be compatible with EMC configurations in test laboratory:

• Power and signal cables should be routed in short and non-parallel paths
• High-current and signal lines should be kept at least 5 cm apart
• Shield grounding should be done as close to device input as possible
• Cable lengths used in laboratory tests (e.g., 1 m, 3 m) should be included in product test plan
• Different cable lengths should be tried in prototypes to observe resonance behaviors (λ/4 effect)

Mechanical and Chassis (Mechanical Shielding)​

21. Does metal enclosure or cover serve shielding function?​

Metal enclosure should serve not only mechanical protection but also electromagnetic shielding (Faraday cage).

• Body should form return path for RF currents and reduce ambient EMI ingress
• Conductive gaskets (EMI gasket), EMI foam, spring contact elements, or dust-tight conductive wicks should be used between cover and body
• Conductive contact surface should be left under paint or anodized layer at screw points
• Shielding effectiveness target: 40 dB or more @1 GHz, 60 dB or more in critical systems

22. Is conductive coating or internal shielding applied in plastic enclosures?​

Plastic enclosures are not naturally conductive; therefore, internal surface shielding is mandatory:

• Silver, copper, nickel, or carbon-based conductive coating should be applied to inner surfaces
• Alternatively, metallized film, copper/aluminum foil, or EMC fabric coatings can be used
• Conductivity: 0.05 Ω/□ or lower (surface resistance)
• Paint layer should be designed to contact chassis at screw mounting points

23. Are spring fingers and screw connections validated for PCB-chassis contact points?​

Low-impedance contact points should be created between PCB and chassis:

• Continuous grounding should be provided using spring finger, EMC pogo pin, spring gaskets, or screw contact
• Resistance target lower than 0.5 mΩ, inductance target lower than 10 nH
• Contact points should be distributed evenly; especially should be located in connector and high-frequency component regions
• Production tolerances and screw tightening torques of connections should be verified with tests

24. Is Faraday cage continuity maintained at case junction points?​

Full electrical continuity should be maintained between different metal parts of the case.

• 360° contact should be provided at weld, rivet, screw, or gasketed joints
• Contact surface under paint or coating should be opened at each joint point
• Each connection point should be 2.5 mΩ or lower in shielding continuity test
• Faraday cage structure should be "closed loop"; broken sections cause EMI leaks
• "Shield continuity path" should be visually verified on case 3D model in EMC design review

25. Are ventilation holes protected with EMI mesh?​

Case ventilation or sound openings can lead to EMI leakage; therefore:

• Hole diameter should be smaller than λ/20 (e.g., 15 mm or smaller for 1 GHz)
• Copper, brass, or aluminum mesh should be used for wider openings
• Mesh surface resistance should be 0.02 Ω/□ or lower, contact resistance to chassis should target 1 mΩ or lower
• EMC mesh filters should also be selected to maintain air flow (CFM) performance
• Conductive fabric or metallized perforated plate solutions can be applied in plastic enclosures

ESD (Electrostatic Discharge) Measures​

26. Is product's ESD test standard (IEC 61000-4-2) and level target defined?​

ESD resistance standard and test levels to which product will be subjected should be clearly determined during design process.

• Test standard: IEC 61000-4-2 Ed. 2.0 (or ISO 10605 for automotive)
• Target resistance level: ±8 kV air discharge, ±6 kV contact discharge
• Target can be ±15 kV air for more demanding environments (industrial, field devices)
• Test plan should be documented with contact points, discharge count, polarity, repetition count, and times

27. Are user-accessible metal parts ESD-safely routed to ground?​

All metal parts that user can touch (e.g., button frame, USB armor, heatsink, screw) should be routed to ESD ground in controlled manner.

• ESD ground (chassis ground) should be separated from signal GND through RC or ferrite
• Direct connection of metal surfaces to signal line is prohibited
• Contact surfaces can be routed to GND through 1 MΩ–10 MΩ resistor; this approach both slows discharge and protects device
• In plastic enclosures, ESD current can be routed to chassis through metallized inner surfaces

28. Are low-capacitance TVS diodes added to critical lines?​

Low-capacitance TVS diodes (Transient Voltage Suppressors) should be used on all user-accessible or externally connected lines:

• Fast data lines (USB, HDMI, LVDS): C less than 1 pF, tclamp shorter than 1 ns, bidirectional TVS should be selected
• Power and control lines: SMBJ, SMAJ, SMDJ series can be preferred
• Protection point should be as close to connector input as possible (less than 5 mm)
• ESD current should flow directly to GND through low-impedance path in PCB layout

29. Are input filters (RC/snubber) selected to limit ESD current?​

RC filters should be used to reduce energy profile of ESD pulses.

• Typical values: 10–100 Ω series resistor + 100 pF–1 nF capacitor
• Maximum suppression should be provided without rise-time degradation in critical signal lines
• Snubber circuits (RC or RCD) are especially preferred in relay, coil, or motor lines
• Filter components should be low ESR/ESL structure; protection should be connected to GND line via shortest path

30. Is antistatic additive or coating application evaluated on plastic surfaces?​

Plastic parts should be designed to prevent static charge accumulation, especially in dry environments:

• Use of plastic granule containing antistatic additive (e.g., BASF Ultradur ESD series)
• Alternatively, surface antistatic coating (e.g., water-based ESD clear coat, static dissipative spray)
• Target surface resistance: 10⁶–10⁹ Ω/□
• Coating thickness should be kept in 10–25 µm range, should not be applied under paint layer

31. Are ESD current paths determined and routed to GND via short path on PCB?​

To prevent uncontrolled distribution of ESD pulses inside device, current paths should be planned in PCB design:

• ESD current should flow directly to GND after TVS, RC filter, and ferrite elements
• This line should be grounded over wide copper area or thick trace (lower than 20 mΩ)
• "ESD return island" can be created on GND plane
• Input line ESD path should not cross-over signal lines
• Multiple via to GND stitching should be applied for high-frequency discharges

EMC Test Preparation and Pre-Validation​

32. Is test board or prototype designed for pre-scan measurements?​

Special pre-scan prototype boards should be prepared at early design stage to predict EMC performance.

• Test board should be a version where functional system is electrically active
• Unnecessary circuits should be disabled to isolate main EMI sources
• RF input/output points, cable ports, and power lines should be accessible appropriately for test setup
• Board should be mounted to provide easy access to laboratory cables and ground connections

This step is the most effective and low-cost method for pre-design risk reduction.

33. Are required port terminations (dummy load, terminator) prepared for testing?​

Appropriate load and termination elements should be prepared to simulate system's real operating conditions in EMC tests:

• Appropriate resistance terminations (50 Ω, 120 Ω) on lines such as Ethernet, RS-485, CAN, USB
• Dummy loads for power outputs (resistive or active load)
• Simulation loads for motor or sensor outputs (RC or RL combination)
• Antenna ports in RF modules should be closed with appropriate 50 Ω terminators

Incorrect or incomplete termination can cause measurement deviation and false positive/negative results.

34. Are noise source monitoring points (RF probe pads) placed?​

RF probe pads should be planned on PCB to find EMI origin during pre-scan:

• Small measurement pads (1–2 mm) should be added to power lines, clock, data bus, and switching regions
• These points should be suitable for testing with near-field probe (H-field or E-field loop)
• Each pad should be in close position with a GND point (for differential measurement)
• After measurement, pads are used to determine corrective actions towards EMI source

This approach is a debug-focused EMC engineering (Design for Testability in EMC) principle.

35. Is cabled test layout (cable harness) appropriate for laboratory conditions?​

For EMC test results to be valid, cable set and layout should comply with laboratory rules:

• Power and signal cables should be at length defined in test plan (e.g., 1 m ±10%)
• Cables should be routed on metal floor at 80 mm height on test table (CISPR 32 requirement)
• Grounding ends of shielded cables should be configured open/closed according to test scenario
• Test harness should have same pinout and topology as production version

36. Are pre-scan results compared with design changes and revision plan created?​

Data obtained from pre-scan tests should be analyzed by design team and converted to revision plan:

• Highest emission frequencies and sources should be determined
• EMI corrections (ferrite, filter, layout change, ground stitching, cable shielding) should be recorded
• Each measure should be tested again to create measure–effect correlation
• Results should be documented in "EMC Corrective Action Report" format

37. Are required reports and configuration documents ready for final EMC tests?​

All documents should be prepared completely before final test:

• Test setup drawing (block diagram + cable routing)
• Device operating modes and test scenarios (idle, transmit, full-load)
• Configuration file (firmware version, hardware revision, power supply type)
• Pre-scan summary report and corrective measures taken
• "Test readiness checklist" specific to test operator

EMI-Effect Mitigation Applications​

38. Are snubber or soft-switching techniques applied in high-frequency power converters?​

High-speed MOSFET/IGBT switchings are the main cause of both dv/dt-sourced EMI and electromagnetic radiation.

• RC snubber or RCD snubber circuits should be added to switching elements
• Alternatively, ZVS (Zero Voltage Switching) or ZCS (Zero Current Switching) topologies should be preferred
• Snubber components should be connected with short, low-inductance lines; loop area should target less than 10 mm²
• Snubber losses should be verified with thermal analysis (P = C × V² × f)

39. Is PWM frequency optimized to not clash with EMI limits?​

PWM switching frequencies should be selected not to resonate with EMC test ranges.

• Typical EMC measurement ranges: 150 kHz – 30 MHz (conducted) and 30 MHz – 1 GHz (radiated)
• PWM frequency should not coincide with boundary regions of these ranges (e.g., around 150 kHz or 1 MHz should be avoided)
• EMI peaks can be distributed with randomized or spread-spectrum PWM techniques (±5–10% jitter)
• Odd-order harmonic cancellation should be targeted for low harmonic energy

40. Are input current harmonics reduced by synchronizing switching cycles?​

Non-synchronization of multiple converters (e.g., DC/DC + motor driver) creates low-frequency harmonics on input line.

• "Phase interleaving" should be applied for each switching cycle (e.g., 180° shift)
• Input filters should be optimized with these phase shifts
• Harmonic current (THD) target 8% or lower in EMI tests (IEC 61000-3-2 Class A/B)
• Modules connected to same supply line should operate with common reference clock

This strategy improves both thermal load distribution and conducted EMI suppression.

41. Are signal cables physically separated from power cables?​

Sufficient physical distance and directional separation should be provided between signal (low-level analog/digital) cables and power cables (high current):

• Minimum distance: 5 cm or more in parallel directions, 90° crossing preferred when possible
• Power cables should be routed along metal surface or chassis
• Signal cables should be close to ground reference, short, and shielded
• Common cable channels should only be used in low-noise class (like CAT 5e signal lines)

42. Are grounding points (PE) connected to single reference in star topology?​

Protective Earth (PE) connections throughout system should be organized with star topology principle:

• PE line of each subsystem should be joined at a single center point (main earth busbar)
• Prevents parasitic currents from spreading to other modules through GND
• Multiple short connections (braid, bonding strap) to chassis can be added for high frequency
• Continuity of all PE points should be 0.1 Ω or lower

EMC Test Result Tracking and Improvement​

43. Are EMC pre-scan reports archived in version-controlled system?​

All pre-scan and intermediate test reports should be stored in a version-controlled documentation system (e.g., Git, PLM, ERP, or QMS).

• Each report should contain date, product code, PCB revision, and test equipment information
• Reports should be archived in PDF + measurement data (CSV/Touchstone) format
• File naming standard (e.g., "EMC_PreScan_PCBv1.2_2025-10-29.pdf") should be applied
• Test results should be associated with production and design revisions for traceability

44. Is root cause and corrective action (RCA/CAPA) record created for test result failures?​

Root Cause Analysis (RCA) and Corrective/Preventive Action (CAPA) records should be prepared for each failed test result.

• Failed frequency band, test mode, and conditions should be clearly stated
• Root cause analysis: should be done with 5-Why, Ishikawa (Fishbone), or 8D methodology
• Corrective actions (e.g., filter added, layout changed, cable direction changed) should be clearly documented
• Effectiveness of action should be verified with re-test result

45. Are developed EMI solution notes (design note) transferred to new projects?​

EMI solution strategies, design notes, and improvement experiences developed in completed projects should be transferred to corporate knowledge base.

• "EMC Design Knowledge Base" or "Lessons Learned Library" should be created
• Each report should be summarized as problem → solution → effect → measured improvement
• These notes should be referenced in Design Review phase of new projects
• This knowledge sharing ensures consistency of EMC performance from project to project