PCB Design Checklist

This checklist is prepared to minimize errors during manufacturing, assembly, and testing phases in PCB (Printed Circuit Board) design. It promotes verifiable designs in terms of both manufacturing (DFM), testing (DFT), and serviceability.

Holes, Pads, and Dimensioning​

1. Hole diameters should indicate finished dimensions after plating in drawings​

Hole dimensions specified in manufacturing files should refer to finished values after plating (copper plating) process. Otherwise, hole may be narrower than intended lead diameter. In accordance with manufacturer tolerances (e.g., ±3 mil), both initial and finished dimensions should be clearly specified.

2. Hole diameters should be at least 10 mils larger than component lead diameters​

Hole-to-lead clearance facilitates solder flow during assembly and reduces thermal stresses. For example, for 0.5 mm lead diameter, minimum 0.75 mm hole is recommended. This difference directly affects manufacturing efficiency especially in THT (Through-Hole Technology) assemblies.

3. Pad sizes should be at least 15 mils larger than hole diameter​

Each pad should be sized to leave sufficient solder area around hole. This increases mechanical endurance, thermal performance and solder wetting quality. Insufficient pad area can lead to problems such as solder cracks or pad lifting.

4. Silkscreen line thickness should be at least 10 mils​

Texts and markings on silkscreen (for example references like R10, C22, D5) should be thick enough not to be easily erased during printing. Minimum 10 mil line thickness maintains readability and meets printing tolerances. Additionally, text sizes should be selected at least 40–50 mils height.

5. All through-hole (THT) components should be aligned on 50 mil grid​

Standard grid usage facilitates design of assembly and test jigs. Additionally, symmetric placement of components reduces alignment errors in automatic placement machines (PTH/AI). 50 mil grid is considered optimum both in terms of engineering standard and visual order.

6. Hole tolerances (drilling, mask, routing, printing) should be specified in drawings​

Manufacturing tolerances of holes — especially for mechanical, solder mask and drilling operations — should be clearly stated in manufacturing files. This information ensures manufacturing according to manufacturer's capacity and reduces revision need. Tolerance ranges are generally around ±2–5 mil.

7. Drill chart should be shown with symbols and dimensions​

Each hole type (for example screw, mounting, signal or via hole) should be defined with symbol and dimension on drill chart. This table is primary reference for production operators and auditors. Complete drill chart should be directly compatible with NC Drill file.

8. Are NC Drill files and photoplot files consistent?​

NC Drill files should match one-to-one with photoplot (Gerber) files sent to production. In pre-production DFM control, hole count, size and locations should be verified. This step is most critical data integrity check — even small inconsistency can make board unmanufacturable.

Printing, Text and Visual Elements​

9. Silkscreen texts should not overlap solder holes, vias or masks​

All silkscreen texts should be positioned in areas that do not interfere with solder pads, vias or solder mask openings. Text overflow onto mask or solder area disrupts readability during printing and can affect solder flow. Therefore, silkscreen–mask DRC control must be enabled in CAD software.

10. All silkscreen texts should be readable in one or two directions​

All texts on board should be aligned to be readable in single direction (left to right) or if necessary in two opposite directions (180° rotation) during production and testing. Randomly oriented texts make component identification difficult during production process. Reading direction standard saves time in both production and quality control processes.

11. Component labels should be aligned left to right, top to bottom​

Reference labels (R1, C5, D10 etc.) should be positioned in same visual order. This order provides visual consistency during assembly and debugging. In complex or multi-layer PCBs, this rule facilitates quick identification of components.

12. Company logo should be on silkscreen layer​

Company logo must be on silkscreen layer for branding and identification purposes. This both identifies board's origin on production line and provides IP (intellectual property) traceability in long term. Logo should be at appropriate size and location not to affect print quality.

13. Company logo should also be added to copper (foil) layer​

Small logo or symbol processed into copper layer provides permanent visibility even after mask. This application is preferred especially in products requiring protection or brand identity emphasis. Logo should be positioned not to interfere with signal paths and ground fills.

14. PCB should have copyright notice​

Short copyright note should be added to board to protect design's intellectual property and identify manufacturing source. For example: © 2025 Hardware Entrepreneurship – All Rights Reserved. This information is valuable both for brand protection and traceability.

15. PCB should have production date (date code)​

Date code expressing production or printing date should be added to PCB. This date is critical for quality control, failure tracking and production lot management. Format is generally YYWW (Year + Week), for example: 25W04 (4th week of 2025).

16. PCB part number and assembly number should be clearly written​

Each board should be labeled with part number (Part No) and assembly number (Assembly No) if any. These numbers facilitate tracking of production variants and ensure finding correct spare part during service.

17. Revision number should be specified on PCB​

Revision number (for example R1.0, R1.1, R2.0) should be clearly written to show which version design belongs to. This information prevents confusion during production and testing phases and facilitates return to previous revisions. Revision changes should also be recorded in "Revision History" table in project documentation.

18. Empty space should be left for assembly revision and serial number​

Appropriate empty spaces (label zone) should be reserved on PCB for operations such as post-assembly marking, labeling or laser printing. This area can be used for serial number, QR code or test approval stamp. During placement, it is important not to interfere with solder mask and be in readable location.

Component Placement and Edge Rules​

19. All polarized components should face same direction​

Polar components (electrolytic capacitors, diodes, LEDs etc.) should be placed facing same direction as much as possible. This practice increases assembly speed, reduces error risk and facilitates direction control in optical inspection (AOI) processes. Additionally, it enables assembly operators and test engineers to interpret board quickly.

20. Components should be at least 0.2" (5 mm) away from board edge​

Components placed too close to board's outer edge may be damaged during panel trimming, routing or test fixture operations. 5 mm distance is accepted as industry standard for both manufacturing safety and mechanical endurance. This area also provides space for panel frame or fiducial positioning.

21. Traces should be at least 20 mils away from PCB edge​

Signal traces close to PCB edge may be damaged during routing tolerances or panel cutting. Leaving at least 20 mil (0.5 mm) distance prevents short or open circuit formations. In high voltage lines, this distance should be increased according to IEC / IPC isolation standards.

22. Mounting holes should be electrically isolated (if necessary)​

Mounting holes should be isolated from ground or signal lines if used screw or standoff is conductive. Holes in contact with metal body can cause EMI or leakage current risk. If isolation required, masked copper ring or non-plated through-hole (NPTH) should be preferred.

23. Mounting holes should be placed on appropriate islands or without isolation​

Mechanical endurance and electrical requirement of mounting holes should be evaluated together. While metallized (plated) connection is preferred for grounding purpose holes, holes used only for mechanical support should be made without isolation (non-plated). In both cases, sufficient copper support (annular ring) should be around hole.

24. Mounting holes should be compatible with mechanical hardware (screw, standoff etc.)​

Hole diameter should be determined according to screw or standoff type to be used. For example, typical hole diameter for M3 screw is around 3.2 mm. Mechanical component placement plans should be verified on 3D CAD model and no alignment problems should occur during assembly.

25. Minimum body distance should be maintained between components​

Minimum clearance should be between all components to allow soldering and test probe access. This distance is generally accepted as at least 30–50 mil (0.75–1.25 mm). Dense placement increases error risk especially during manual assembly or rework.

26. Safe distances should be maintained for high current or high voltage traces​

Traces carrying high current should be appropriately wide to prevent heating; high voltage lines should be positioned at minimum distance from other traces according to standards. This value should be determined according to standards like IPC-2221 or UL-60950. Insufficient distance can cause partial arcing or surface leakage currents.

27. Adequate trace clearance and isolation should be provided in high voltage circuits​

In high voltage circuits, creepage (surface distance) and clearance (air distance) values should be carefully calculated. For example, minimum 3.2 mm isolation distance is recommended in 230 V AC circuits. Isolation slots, slots or optical isolation can be used on critical lines. These rules are mandatory both for user safety and certification compliance.

Electrical and Grounding Rules​

28. Ground (GND) planes should be used at appropriate places​

Ground planes are critically important both for EMI (Electromagnetic Interference) suppression and signal integrity. There should be uninterrupted reference plane under all high frequency signals. Additionally, ground plane both reduces emission by surrounding signal traces like shield and minimizes return current paths. Uninterrupted GND surfaces also increase board's thermal conductivity.

29. Analog and digital grounds should be combined only at single point​

Analog (AGND) and digital (DGND) grounds should be kept separate to prevent noise and measurement errors; should be combined at system's single reference point (star point). This point is generally selected at location close to ADC, DAC or power input. Incorrect combination causes digital currents to pass through analog measurement lines and causes measurement errors.

30. Shielding and protection should be applied for high frequency circuits​

RF, oscillator or high-speed data circuits should be protected with metal shield (shield can) or copper partitioned areas against EMI effects. Additionally, electromagnetic emission can be reduced by applying coaxial or differential routing on critical signal lines. In such circuits, component placement should be carefully planned for shielding efficiency.

31. EMI / RFI filters should be placed closest to input / output points​

Filter elements (for example ferrite bead, RC filter, common-mode choke) should be positioned at shortest distance to these points to suppress electromagnetic interference (EMI/RFI) effects that may occur at connector or cable inputs. Remote placement of filters causes parasitic energy to leak into circuit. This is critical requirement both for certification (CE/FCC) and system stability.

32. Thermal relief should be applied to heat-generating components​

Thermal relief should be used on pads under heat-producing elements (for example regulator, power MOSFET, driver ICs). This structure both provides temperature balance during soldering process and reduces component's thermal stress. In dense copper areas, heat dissipation should be provided in controlled manner instead of direct connection (solid fill).

33. Solderability should be preserved using thermal reliefs on power layers​

When wide power lines are directly connected to large copper areas, heat sinking during soldering can cause solder not to stick. Therefore, thermal bridge (thermal relief) structure should be used on pads connected to power planes. Additionally, adding slot or separator between large copper areas improves thermal balance.

34. Multiple via connections should be provided for high current paths​

Parallel vias should be used for high current transitions between layers. Single via can cause high resistance and temperature increase. At least one 0.3–0.4 mm via is recommended per 1 A current; multiple via or "via stitching" should be applied for higher currents. This approach increases current carrying capacity while balancing thermal distribution.

35. Current-carrying trace widths should be calculated according to current to be carried​

Width of traces carrying high current should be calculated according to IPC-2152 standard. For example, minimum 25–30 mil width is recommended at 35 µm copper thickness for outer layer trace carrying 1 A current. Insufficient trace width can lead to overheating and carbonization. Additionally, thermal vias and copper fills should be used as support on high current density lines.

Testability (DFT)​

36. There should be test pad or test via for each net​

At least one test point (test pad or test via) should be designed for each electrical connection (net) on board. This approach enables easy application of in-circuit test (ICT) or flying probe tests. Each test point should be 0.8–1.2 mm diameter, suitable for contact with probe needle. This practice speeds up post-production error detection and provides great convenience during service phase.

37. Test pads should be at least 200 mils away from board edge​

Test points should be placed not to be damaged from panel cutting or mechanical fixtures. Test pads positioned too close to board edge may be affected or break from routing operations during production. Therefore, it is recommended to position test points at least 0.2 inch (5 mm) inside from PCB edge.

38. Test points should be labeled for power, GND and critical signals​

Test pads should be labeled separately for all power lines, ground (GND) points and systemically critical signals (for example RESET, CLK, UART_TX, VCC_MAIN). These labels facilitate signal identification during testing and reduce incorrect measurement risk. Labels should be clearly shown on silkscreen or mechanical drawing layer.

39. Ground test points should be sized to be accessible with oscilloscope clip​

Ground (GND) test points should have size and shape that can make secure connection with probe or alligator clip. Generally, 80–100 mil diameter circular pad is used. Since these access points are used as reference in high frequency measurements or noise analyses, solid connection surface is of great importance.

40. Extra connector pins should be accessible during testing and prototype phase​

Unused pins in design or reserved for future expansion/testing purposes should be made accessible through test header or temporary connector. This approach provides quick modification opportunity during prototype development and debugging. Additional pins should be clearly labeled on PCB and marked as "N/A" in production variants.

Signal Integrity and High Frequency​

41. Signal paths should be short and direct​

All signal paths should be routed as short, direct and with minimum via count as possible. Short paths preserve signal integrity by reducing both parasitic capacitance and inductance. Especially on high-speed lines (clock, USB, SPI, LVDS etc.), each via crossing creates impedance disruption point; therefore via usage should be limited.

42. Series terminators should be placed close to signal sources​

Series termination resistors used on high-speed or reflection-risk lines should be placed at closest point possible to signal source (driver). This resistor attenuates energy reflected along line and stabilizes waveform. Typically selected in 22–100 Ω range and applied only at source end.

43. High frequency crystals should be placed close to PCB and body grounded​

Crystal oscillators should be placed at shortest distance possible to microcontroller they are connected to. Long lines increase phase noise and decrease start-up stability. Additionally, crystal's body and surrounding guard rings should be grounded and signal lines kept short. Ground ring (guard ring) use reduces parasitic capacitive interaction.

44. High frequency traces should not pass under sensitive components​

RF, clock or fast digital lines should not be routed under sensitive analog components such as ADC, op-amp, reference voltage sources. These lines should be passed over ground shield (ground plane) on lower layers. Otherwise, electromagnetic field coupling occurs causing measurement errors or instability.

45. Analog / digital signals should be routed not to mix​

Paths where analog and digital signals pass should be physically separated, separate routing zones should be created if necessary. Analog paths should not run parallel with digital clock or high frequency lines. This separation lowers noise floor in analog signals and increases ADC/DAC accuracy.

46. Sensitive signal lines should be kept away from power lines​

Power lines, especially those carrying high current, are electromagnetic noise sources. Low-level signals such as ADC inputs, sensor signals or reference lines should be separated horizontally and vertically from these lines. Separate routing layers or guard trace should be applied if necessary.

47. SMD pad shapes should be designed appropriately and according to manufacturer recommendation​

SMD component pad sizes, shapes and spacings should be created according to manufacturer datasheet. Especially for fine-pitch ICs (QFP, QFN, LGA), manufacturer recommended "land pattern" dimensions should be followed. Excessively small pad creates solder not sticking risk, while large pad increases solder bridge risk. Correct pad geometry is determining factor for solderability and assembly quality.

Visual, Assembly and Manufacturing Details​

48. All texts on silkscreen should be readable even after board is assembled​

Texts on PCB should be visible even after components are placed. Especially reference numbers (R1, C5, U10 etc.) should be easily readable during debugging and maintenance processes. Texts placed under large components (for example connector or display modules) should be moved to edge areas instead.

49. Pin 1 direction should be clearly marked on all integrated circuits​

Pin 1 position on each IC should be clearly shown on silkscreen layer. This greatly reduces assembly errors and reverse soldering risk. Pin 1 mark should be compatible with triangle, dot or notch direction in integrated symbol.

50. Corner pins should be numbered on high pin count ICs and connectors​

Corner pins (for example 1, 25, 50, 75, 100) should be numbered on silkscreen on integrated circuits above 64 pins or long connectors. These numbers facilitate probe alignment during assembly and testing phases. Additionally, they prevent pin counting errors during manual soldering or debugging.

51. Every 5th or 10th pin should be marked on long pin rows​

Marking every 5th or 10th pin on long connection elements such as header, socket or pin rows increases assembly accuracy. This mark can be in form of number, dot or short line. Providing visual reference increases both production speed and quality.

52. SMD component directions should be consistent (either all horizontal or all vertical)​

SMD components of same type (for example resistors, capacitors, diodes) should be aligned on single axis if possible. Consistent placement reduces operation time for automatic placement machines (pick & place) and facilitates visual recognition in AOI systems. This standard also reduces error risk during rework.

53. Components should be accessible for rework after assembly​

SMD and THT components should be accessible to be replaced or measured when necessary. Surroundings of critical circuit elements (for example microcontroller, power regulator, connectors) should not be placed densely. This area should be planned to allow access for soldering iron tip, hot air gun or thermal pencil.

54. Removal of one component during assembly should not affect others​

It should be ensured that neighboring components are not affected thermally or mechanically during replacement of component. Minimum clearances between components reduce heat dissipation and solder mask damage risks during rework. Thermal barrier or protective coating strategies can also be applied in areas requiring rework.

55. Standoff should be used for hot-running components​

Mechanical riser (standoff) or air gap should be left under components working at high temperature such as power transistors, rectifiers or linear regulators. This method both prevents board deformation and increases thermal distribution. Additionally, thermal via arrays can be added to conduct heat to lower substrates.

56. Potentiometers should be adjusted to increase clockwise​

On adjustable components (for example trimpot, potentiometer), clockwise turning direction should correspond to value increase. This provides intuitive use during maintenance and calibration operations and prevents reverse adjustment errors. Adding direction indicator on silkscreen is recommended.

57. Mounting holes should be positioned at appropriate spacing for test equipment​

Fixture, apparatus or cabinets compatible hole spacings should be designed for mounting and testing. If mounting holes are placed symmetrically according to board's mechanical center, production error probability decreases. These dimensions should be shared in advance with test equipment supplier or manufacturer.

58. Panelization should be compatible with production and test equipment​

Panel layout (array) should be planned according to both production line capacity and test fixtures size. Fiducial marks, break channels (mouse bites) or V-cut lines should be correctly placed at panel edges. Incorrect panel configuration can cause alignment errors on assembly line.

59. PCB panels should be appropriately sized for test fixtures​

Panel size should mechanically fit perfectly into test fixture (bed-of-nails, flying probe). Alignment holes for alignment of pins on fixture should be in correct position. Panelization design should be verified in coordination with manufacturer and test equipment supplier.

Manufacturing Files and Quality Documents​

60. Netlist should be checked automatically and manually​

Netlist obtained from CAD software should be verified with both automatic (ERC/DRC check) and manual review. While automatic check catches connection errors; manual review detects naming or variant-related errors. Netlist should be one-to-one consistent with Gerber and BOM files sent to manufacturer.

61. There should be no single-connected (floating) nodes in netlist​

Unconnected (floating) nets or single-pin nodes can create post-production open circuit or potential EMI sources. Therefore, all nets should be associated with component or reference point. All floating nodes should be cleared in CAD reports.

62. CAD Design Rule Check (DRC) should be completed​

Before production file is received, DRC (Design Rule Check) should be completely executed and all errors should be resolved. Production parameters such as trace width, spacing, pad clearance, via size, mask alignment and hole position should be checked according to manufacturer standards. File submission should not be made without evaluating all DRC warnings.

63. Hole origin should be defined as reference tooling hole​

Tooling hole (reference hole) positions to be used in production and test processes should be clearly defined in PCB drawing. These holes serve as reference for panel alignment and test fixtures to sit correctly. Origin point should be consistent with panel layout.

64. Checkplot outputs and photoplot files should be sent together​

In file set sent to manufacturer, checkplot (visual check output) and photoplot (production image) should be included for each layer. Checkplot is used for final verification before production and contains meta information such as date, revision, file name. This ensures that correct file is processed by manufacturer side.

65. NC Drill and photoplot formats should be specified​

NC Drill and Gerber (photoplot) file formats (for example Excellon, RS-274X, Gerber X2) should be clearly specified to manufacturer. Format incompatibilities can lead to hole layer alignment errors. Format version, unit of measurement (mm/mil) and coordinate zero point should be defined in file description note.

66. Drill plot should be cross-checked with NC Drill file​

Hole sizes, quantities and symbols should be consistent between drill chart and NC Drill file. This check before production eliminates incorrect diameter or missing hole risk. Additionally, plated / non-plated holes should be specified in separate tables.

67. If maskless copper is desired, it should be noted​

If maskless copper is requested in certain areas (for example on test pads or heat distribution areas), this information should be clearly stated in production notes. Misinterpreted mask settings can lead to solder bridges or oxidation problems.

68. PCB thickness, material type, copper weight should be specified​

PCB's total thickness (for example 1.6 mm FR-4), copper weight (for example 1 oz/ft²) and material type (for example TG150, Rogers, Polyimide) should be clearly stated in manufacturer documentation. This information is mandatory both for mechanical compliance and thermal performance.

69. Trace width and gap geometry should be clearly specified​

Minimum trace width, trace spacing (clearance) and via sizes should be reported to manufacturer in compliance with DRC parameters. These values are generally written in technical note as "Minimum Trace/Space = 6/6 mil" format. Insufficient information can lead to incorrect assumptions by manufacturer side.

70. Drill report and aperture table should be added to outputs​

Drill report containing all hole diameters and quantities and aperture table should be added to production package. These tables are necessary for manufacturer to verify in CAM software. Missing aperture information can cause incorrect pad sizes during production.

71. Photoplot files should be checked with viewer​

Gerber files should be viewed and verified with Gerber Viewer or CAM editor before sending to manufacturer. Errors such as incorrect layer order, inverted mask or missing drill layer can be easily detected at this stage. This is one of most critical manual check steps of DFM process.

72. Test coupons containing minimum geometry should be added to PCB​

Test coupon should be at one corner of panel for production control. This coupon enables testing of parameters such as minimum trace width, hole diameter and copper plating quality. Test coupons are industry standard for monitoring production quality (for example IPC-2221, IPC-6012).

73. Coupon should contain minimum trace spacing, pad size and hole dimensions​

Test coupon should represent smallest geometric dimensions used on board. This way, manufacturer can test workability of actual board. For example: information like "Min Trace = 4 mil, Min Hole = 0.25 mm" should be added on coupon.

74. Coupon should have antistatic warning, QC label and board number​

Each test coupon should have antistatic warning (ESD caution), quality control (QC Passed) label and panel number. This information ensures traceability of production lots and can be matched with quality documents. In serial production, this labeling system is evaluated as part of quality standard.

Design Compliance and Functionality​

75. IC pin count should match between layout and schematic​

Pin count of each integrated component should match one-to-one between schematic and PCB layout. Missing pin, extra connection or incorrect numbering are among most difficult errors to repair after production. This check should be verified with CAD software's "pin consistency check" feature and manual review.

76. Vias should not be placed under metal film resistors​

Since metal film resistors work at high temperature, vias under them can cause thermal imbalance during soldering. Additionally, heat transfer from inside via can cause deviations in resistance tolerance. Therefore, via placements should be planned not to correspond under component body.

77. Traces with solder bridging risk should be checked​

Especially in fine-pitch ICs and SMD components, areas carrying solder bridging risk should be reviewed. Mask spacing (solder mask clearance) and trace clearances should be higher than manufacturer minimum values. Visual check with 3D solder mask preview before production is recommended.

78. Make sure there are no dead-end traces​

Unconnected or "dead-end traces" that do not reach any pad can create production error or unnecessary parasitic source. These traces generally result from forgotten connections after revision. These situations should be cleared with Gerber preview or DRC report.

79. Power and GND short circuit should be tested​

In final verification before production, it should be ensured that there is no unwanted short circuit between VCC–GND lines. This test should be done with CAD software's "net connectivity check" feature, confirmed with ohmmeter on prototype board if necessary.

80. Vcc, Vdd, Vss, GND net separation should be compatible with schematic​

Power lines defined with different names (for example Vcc, Vdd, 3V3, 5V0 etc.) and ground references (Vss, GND, AGND) net names on PCB should match one-to-one with their names on schematic. This consistency plays critical role in power architecture verification and automatic DRC analysis.

81. Is layer structure (stack-up) confirmed with manufacturer?​

PCB layer structure (for example 4L, 6L) should be compatible with dielectric thickness, copper thickness and impedance targets provided by manufacturer. Stack-up agreed with manufacturer should be clearly stated in production notes and changes should be entered into revision table.

82. Is blind / buried via use compatible with manufacturer capabilities?​

In designs using blind or buried vias, it should be verified that manufacturer supports this technology. Via depth, diameter ratio and layer connection should not exceed manufacturer's technical limits. Otherwise, production cost increases or error rate rises.

83. Are fiducial, panel break-tab, mouse-bite and V-cut placements verified?​

Fiducial marks on panel, panel break channels (V-cut or mouse-bite) and break-tab positions should have been shared with manufacturer. Incorrect placement of these elements can disrupt assembly machine alignment. Fiducials should be on copper open surface and in symmetric position.

84. Is production barcode and QR code area defined for PCB panel?​

Barcode or QR code area should be reserved on panel or board for production traceability. This area can contain data such as production batch, date, revision and serial number. Text position should be compatible with printing or laser marking systems.

85. Are thermal balance zones suitable for reflow / wave solder profile provided?​

Large copper areas on PCB should not create thermal imbalance during soldering. Thermal balance zones suitable for reflow or wave profile should be planned; thermal bridge (relief) should be applied on large pads if necessary. This balance increases solder quality and prevents cooling cracks.

86. Do Board Outline and Keep-out boundaries overlap with manufacturer DXF?​

PCB outer lines (board outline) and component keep-out areas should be fully compatible with mechanical DXF drawing provided by manufacturer. This check prevents mechanical part overlaps and panel alignment problems. 1:1 scale verification should be done with mechanical CAD.

87. Is via-in-pad region filling / capping requirement specified?​

In cases where vias are located inside pad for signal integrity or thermal management purposes, via filling (fill / cap) requirement should be clearly stated to manufacturer. Incorrect via processing can lead to solder absorption or void formation. Additionally, epoxy or copper plating method used in these areas should also be defined.

88. Is impedance control measurement coupon added for critical impedance lines?​

Impedance test coupon should be added on panel for differential or controlled impedance lines (for example USB, HDMI, Ethernet). This coupon enables measurement of actual impedance value after production. Coupon should contain same layer and geometry conditions for testing.

89. Is on-panel "golden sample" test coupon marked with revision number?​

"Golden sample" (reference test board) on production panel should be marked with relevant revision number. This ensures complete traceability between production batch and test results. Test boards without specified revision can cause confusion in quality control.

90. Is 3D step model clash-free with mechanical CAD?​

PCB's 3D step model should be overlaid with mechanical CAD (for example SolidWorks, Fusion 360, CATIA) and checked. Component heights, mounting holes, enclosure and connector alignments should be tested. This verification enables detection of mechanical incompatibilities before production and shortens prototype time.