Schematic Design Checklist

This checklist is prepared to ensure readability, manufacturability, and testability of schematic design. Each item includes brief explanations of what should be considered during implementation.

Visual Structure and Page Information​

1. Are information blocks complete?​

Every schematic page should contain essential information blocks such as; project title, customer or product name, module code, version (or variant) number, design engineer name, GitHub or source control address, page size, date-time stamp, page number, filename, and copyright notice. These metadata ensure traceability in production and audit processes, facilitate revision management, and establish common reference point across engineering disciplines.

2. Are schematic scale and readability appropriate?​

Symbol sizes, text heights, pin and net names should be easily readable. Design where values and references can be clearly selected saves significant time during both production and debugging. Excessively compressed, overlapping, or symbols drawn at different scales are among most common sources of design errors.

3. Is page layout flow-appropriate (left entry, right exit)?​

Signal and power flow should generally be arranged from left to right, top to bottom. This layout allows schematic to create natural reading direction and makes logical connections easier to follow during review. Block diagram-like flow helps systematic perception of design.

4. Are entry page and index / revision notes available?​

Project's first page should introduce general system architecture, sub-modules and variants if any. Also, page indexes, symbol legend, abbreviations used and revision history should be included here. This page provides quick orientation especially for newly joined engineers or external auditors.

5. Is there large section headings and page number standard?​

Each page should clearly indicate sub-system it contains (for example "Power Regulation", "MCU Interface", "RF Front-End" etc.). Page naming standard is critical for both version control and intra-team communication. Consistency in numbering increases sustainability of documentation.

6. Are cross-page transition references clear?​

Off-page connectors, data buses and net names should be clearly marked with numbers of target pages they connect to. This practice significantly reduces signal tracing time especially in multi-page projects and preserves circuit logic integrity.

Naming, Symbols and References​

7. Are reference codes given to all components?​

Each component should have unique reference code (for example R1, C10, U3). These codes provide traceability both in BOM (Bill of Materials) tracking and during assembly. Missing or repeated references are one of most common causes of production errors. Make sure to verify this compliance in post-revision checklists.

8. Is reference code format standard?​

Format of reference codes should comply with standard defined within team. For example; Q01, R105 or U8A / U8B format should be preferred for multi-part integrated circuits. Consistent naming ensures error-free operation in processes such as automatic test systems, netlist extraction and BOM integration.

9. Are unit and format standards maintained?​

International formats should be used in writing electrical values: 3.3V → 3V3, 2.2uF → 2u2 etc. Dot (.) character should not be used in net names or values because some CAD tools may interpret it as decimal separator. Consistent format guarantees data integrity in both schematic and PCB stages.

10. Do symbol libraries have correct pin mapping?​

Especially for custom or externally added parts, whether pin numbers on symbol are compatible with manufacturer datasheets must be checked. Incorrect pin matching is one of most difficult and costly errors to detect in circuit board production.

11. Do symbols have necessary parameters?​

In critical components, parameters such as minimum/maximum operating voltage, temperature range, current limit or package type should be specified in schematic symbol or description field. This information speeds up engineering verification in design reviews and DRC (Design Rule Check) processes.

12. Does manufacturer name not appear on schematic (generally)?​

Schematic designs should be manufacturer independent. Manufacturer name, MPN (Manufacturer Part Number) or supplier information should only be kept in BOM document. This separation facilitates alternative component selection and supply management.

13. Do library elements have datasheet / link fields?​

Each symbol or component library should have field for datasheet link. This way, designer can instantly access component specifications and minimize misuse risk. Additionally, it speeds up information sharing within team and supports continuity of engineering process.

Connection Rules and Net Management​

14. Are pin directions correct? (IN / OUT / I/O / POWER / GND)​

Direction of each pin should be defined according to component's function. Correct classification of input, output or bidirectional (I/O) pins is critical for EDA tools' ERC (Electrical Rule Check) operations. Incorrectly defined pin directions can cause short circuits or driver conflicts.

15. Are all unused pins terminated with "NC"?​

Unconnected (floating) pins can create unwanted noise, random behavior or unexpected power consumption in circuit. All unused pins should be clearly marked with NC (No Connect) label or properly grounded according to datasheet guidelines.

16. Are supply and GND pins explicitly connected (no hidden pins)?​

Some CAD tools use hidden power pins (hidden power pins) especially in integrated circuits. When these pins are not visible, power distribution errors may easily go unnoticed. All supply (VCC, VDD etc.) and ground (GND) connections should be explicitly shown on schematic.

17. Are power nets named in standard format with +/− sign?​

Power lines should be named consistently: for example +3V3, −1V8, VBAT, +5V_USB etc. This standardization prevents incorrect voltage connections and makes power distribution topology easy to understand.

18. Are data bus directions and sequences consistent at both ends?​

In multi-bit bus lines (for example D[0..7, A[0..15) or connectors, bit order and direction should be exactly same at both ends. Reversed or shifted bit arrangements create error sources at system level that are difficult to recover.

19. Are related signals (UART, I²C, SPI etc.) grouped?​

Grouping related signals together facilitates both readability and debugging. For example, UART_TX/RX, SPI_MOSI/MISO/SCK/CS, I2C_SCL/SDA lines should be shown physically close and visually together. This approach maintains order in schematic and shortens review time.

20. Are off-page data buses clearly shown with edge labels?​

Signals extending to different pages should be marked with off-page connector or net label labeled at page edge. This enables quick tracking of signal flow in multi-page projects and guarantees connection consistency.

21. Are appropriate pull-up / pull-down resistors available on open-collector / open-drain lines?​

Such lines become unstable when logical level is not determined with external resistors. Make sure that pull-up or pull-down resistors are selected at correct positions and appropriate values. This is especially critical on I²C, interrupt or reset lines.

22. Are active-LOW signals marked with line (¯)?​

Active-LOW signals should be indicated with line above their names (e.g., RESET̅, CS̅) or with "_N" suffix at end (RESET_N). This notation standard prevents misunderstanding of logic direction and ensures consistency across design documents.

23. Does reset line have reliable design?​

Reset line should ensure deterministic system startup. Measures such as RC-based delay circuits, supervisor ICs or manual reset button should be implemented to prevent random states during power-up. This design discipline is one of most critical factors determining stability especially in microcontroller-based systems.

Power Architecture and Bypass/Decoupling​

24. Do all integrated circuits have bypass capacitor at each supply pin?​

Each integrated circuit should have bypass (decoupling) capacitors positioned as close as possible to its supply pin. Generally, 100 nF ceramic capacitor is added for each pin; in addition, appropriate value bulk (for example 1–10 µF) capacitance is connected in parallel to ensure overall line stability. These elements suppress high frequency noise and preserve supply line stability during sudden current demands.

25. Is bypass capacitor placement intent annotated on schematic?​

It should be clearly noted on schematic that each bypass capacitor needs to be placed in physical closest proximity to pin it supplies. This is not reminder but design rule for PCB designers. Remotely placed bypass elements largely lose their effect and can lead to EMC problems.

26. Is separate power path provided for analog blocks?​

Sharing same power line between analog and digital circuits significantly increases signal noise. Therefore, analog and digital supply paths should be separated, connected to each other at appropriate point with ferrite bead or RC filter. This separation is basic criterion determining measurement accuracy especially in ADC, DAC, op-amp or RF circuits.

27. Are LDO input/output capacitance conditions satisfied?​

Low-dropout regulators (LDO) require specific capacitance and ESR (Equivalent Series Resistance) values. Minimum input and output capacitor values specified in manufacturer datasheet for each LDO should be provided; ESR limits should be considered. Inappropriate capacitor selection can cause oscillation or unstable output voltage.

28. Is power sequencing and energization scenarios defined?​

In systems with multiple voltage lines, power-up sequence should be clearly defined. Some integrated circuits do not tolerate raising other voltage line before certain voltage line is active. Additionally, how system will behave in case of brown-out or sudden voltage drops should also be specified in design notes. This information is vital for both firmware and hardware reliability.

29. Is total current budget (worst-case) calculated?​

Maximum current consumption of all system components should be summed according to worst case scenario and power supply capacity should be selected accordingly. This analysis should include not only average current but also instantaneous (peak) demands. This calculation is mandatory for both regulator selection and thermal management.

30. Are resistor power values verified?​

Power endurance (P = V²/R) of used resistors should be calculated and appropriate package size should be selected. For long-term stability and reliability, resistors should work in 50–70% range of their nominal power. Overloaded resistors create value loss and thermal damage over time.

31. Are voltage divider / pull-up / pull-down currents calculated?​

Current flow in voltage divider circuits or level determining resistors should be correctly calculated. Too low currents make inputs susceptible to noise, while unnecessarily high currents increase power consumption. Especially in battery-powered systems, these resistors directly affect energy efficiency.

Protection, Safety and Compliance​

32. Are off-board interfaces protected against ESD?​

All lines in contact with external environment (for example USB, HDMI, UART, buttons, sensor connectors) should have ESD (Electrostatic Discharge) protection. Especially connectors and metal surfaces that can be touched by user should be protected with TVS diode or protection resistors against transient voltage pulses. This measure significantly reduces both hardware failures and field-sourced warranty costs.

33. Are rules established for high voltage / current lines?​

For power lines, trace width, fuse, clearance and creepage distances should be checked according to design standards. Standards such as IPC-2221 or UL-60950 can be referenced. These criteria are mandatory not only for safety but also for long-term thermal endurance. Additionally, thermal vias and copper thickness should be sufficient on high current lines.

34. Is transient resistance provided for automotive-class modules?​

In automotive applications, supply lines can be exposed to sudden voltage pulses (load dump) between 60–100V. Therefore, protection should be done with transient voltage suppressor (TVS) diodes, LC filters and appropriate fuse elements. Test conditions should be defined by referencing ISO 7637 or ISO 16750 standards. This measure guarantees reliable operation of device in interaction with vehicle's electrical system.

35. Is CE / FCC / RoHS compliance checked?​

CE (Europe), FCC (USA) and RoHS (hazardous substance restriction) requirements should be taken into account during product design phase. Although EMC (electromagnetic compatibility) and safety requirements are tested after production, design controls made at early stage prevent costly revisions. Appropriate component selection, grounding strategy and filtering topology play determining role in this process.

36. Are connector / socket mechanical compatibilities verified?​

Mechanical seating dimensions, keying switches, PCB thickness compatibility and matching counterparts of all connectors and sockets should be verified according to datasheet. Wrong direction or tolerance difference causes high failure rates in field assembly. Especially to prevent confusion on production line, connector type and direction should be clearly specified on schematic.

37. Is status of mechanical fixing pins defined?​

Mechanical fixing pins present in some components (for example large connectors, keypads, modules) can be connected to ground (GND) line or electrically isolated. This decision should be clarified in design phase and clearly shown in PCB production files. Free or incorrectly connected fixing pins create risk in both EMC and mechanical endurance.

Analog, RF and Signal Integrity​

38. Are op-amp stability and common-mode range verified?​

In op-amp circuits, stability, gain-bandwidth (GBW), slew rate and behavior parameters against temperature changes should be checked. Phase margin and oscillation risk should be analyzed according to feedback topology used. Additionally, input signals should remain within op-amp's common-mode voltage range; otherwise linear operation is disrupted. These checks are critical for accuracy especially in sensor interfaces and measurement circuits.

39. Is oscillator / clock energization checked?​

Power lines of all oscillators, crystals and clock sources should be filtered according to manufacturer recommendations and supply stability should be ensured. Weak supply or insufficient bypass can lead to clock jitter and communication synchronization errors. This situation creates systemic instability especially in MCU, RF transceiver or high-speed communication (for example USB, Ethernet) lines.

40. Are crosstalk and parasitic effects evaluated?​

Unwanted signal transition (crosstalk) between analog, digital and high frequency lines should be analyzed. Long parallel traces should be avoided, differential routing or ground reference line should be used when necessary. In impedance-controlled lines, trace lengths and dielectric thickness should also be reviewed in terms of signal integrity. This analysis is vital especially at ADC inputs, RF signals and high-speed data lines.

41. Is via stitching annotated for RF lines?​

RF traces, especially at frequencies of 2.4 GHz and above, should be surrounded with via stitching (shielding with grounding holes) technique to protect from environmental effects. This application reduces RF leakage between PCB layers and preserves impedance continuity. This requirement should be clearly noted on schematic; otherwise it may be overlooked during routing.

42. Are FET gate drives and overvoltage conditions examined?​

Gate lines of MOSFET or similar power elements should be evaluated in terms of both driver resistance (gate resistor) and overvoltage protection. Oscillations that may occur due to gate capacitance during sudden transitions create risk in terms of both EMC and thermal stress. Therefore, snubber circuit, TVS diode or zener clamping solutions should be applied when necessary.

43. Are power semiconductors evaluated in failure scenarios?​

Energy discharge scenarios that may occur on MOSFET, IGBT or driver integrated circuits during failure conditions such as short circuit, load disconnection or overheating should be analyzed. Thermal endurance, SOA (Safe Operating Area) limits and protection topologies (for example current limitation, overheating protection, fuse) should be defined. These checks form foundation of long-lasting and safe power system.

Interfaces and Communication​

44. Are UART / SPI / I²C timing and level compatibilities verified?​

All communication lines should be checked according to timing and logic level (voltage level) requirements of connected devices. For example, while sensor works at 3.3 V logic level, microcontroller may be at 5 V level — in this case, level shifter or resistor divider should be used. Additionally, data transitions should be compatible with setup/hold times and maximum clock frequencies of each device. This check eliminates most common source of communication errors.

45. Is baud and clock selection correct?​

In serial communication protocols (especially UART), selected baud rate value should be compatible with microcontroller clock frequency and error rate should be low. Baud deviations above 2% can cause problems especially with long cables or low-tolerance receivers. In synchronous protocols like SPI and I²C, clock frequency should be determined according to maximum speed parameters of connected devices. Correct speed selection directly affects both data integrity and power consumption.

46. Are open-drain / pull-up designs reviewed?​

On I²C or shared line using open-drain interfaces, appropriately valued pull-up resistors should be on line. If resistance values are too low, line becomes susceptible to noise, if too high, signal rise time extends. Correct resistance selection is critically important for bus integrity and communication reliability. Additionally, safe pull-up line voltage should be defined between devices working at different voltage levels.

47. Is small filtering (33 pF etc.) provided on I/O lines?​

Small capacitors (for example 22–47 pF) added in series to digital I/O lines increase system's EMI/EMC resistance by suppressing high frequency noise. Such filtering elements increase communication safety especially in long cable connections or external sensor lines. However, capacitance value should be carefully selected not to distort signal rise time.

48. Are analog lines distant from digital lines?​

Analog signals, especially low level measurement lines (for example sensor outputs or ADC inputs), should be physically separated from digital clock or high frequency signals. This separation should be maintained in PCB routing strategy and analog lines should preferably work on separate reference plane (AGND). This measure reduces parasitic transitions and increases measurement accuracy.

Variant Management and Modularity​

49. Is part populate/unpopulate status marked on variant boards?​

If multiple product variants (for example "Pro", "Lite" or "OEM" versions) are managed on same PCB, part populate/unpopulate (DNP – Do Not Populate) status should be clearly indicated for each variant. This information should be defined both on schematic and in variant-based BoM (Bill of Materials) document. Clear markings prevent confusion during production and ensure error-free assembly. Additionally, if variant management feature is used in CAD systems, production files should be created separately for each configuration.

50. Are module connector assembly conditions specified?​

If external modules (for example GSM, Wi-Fi, GPS, sensor or power modules) are used on board, assembly direction, height, soldering type (SMT / TH) and mechanical support requirements of these connectors should be clearly specified on schematic or in note area. This information ensures correct positioning during production and reduces errors especially during manual assembly or prototype production.

51. Is pin sequencing consistent on different PCBs?​

In systems containing multiple PCBs or sub-modules, pin arrangement of same interface or connector should be consistent. Even small differences in pin order can lead to serious errors and damage in cable sets or test jigs. Therefore, establishing common connector standard across all sub-boards provides long-term maintenance, production and service convenience.

52. Are 0Ω jumpers added to critical lines?​

Using 0 ohm resistor (jumper) on critical or unstable signal lines provides design flexibility. These elements allow quick changes for test, measurement or alternative connection scenarios in subsequent revisions. Additionally, they support easy modification on board during production variants or debugging processes.

Component Selection and Lifecycle​

53. Are polar component directions correct?​

Directions of all polar (polarized) components (for example electrolytic capacitor, tantalum capacitor, diode, LED) should be correctly defined on schematic and PCB. Reverse feeding can cause permanent damage, explosion or board damage especially in electrolytic and tantalum capacitors. Therefore, polarities should be clearly marked on both symbol and placement layer, added to production files as clear note.

54. Are component voltage / current / temperature conditions compatible?​

Maximum operating voltage, current and temperature range of each component should be compared with circuit's worst-case conditions. Continuous operation of components at limit values significantly reduces reliability. To leave safety margin in design, components should generally be used at around 70–80% of nominal conditions capacity. Additionally, derating calculations should be made in high temperature environments.

55. Is Darlington output drive appropriate?​

Darlington transistors or similar high-gain driver structures sometimes create higher saturation voltage (VCE(sat)) than expected. Therefore, if load voltage or power distribution is critical, suitability of Darlington configuration should be checked. Alternatively, more efficient result can be obtained by preferring MOSFET-based driver circuits. This evaluation is especially important in motor, relay or solenoid drivers.

56. Is multi-gate logic component allocation correct?​

In integrated circuits containing multiple logic gates (for example 74HC00, 74HC14), function of each gate should be clearly defined and no idle gate should be left in design. Unused inputs should be connected to fixed level with pull-up or pull-down resistors according to manufacturer recommendations. Idle logic inputs can lead to random behavior and fluctuations in power consumption.

57. Is part availability checked?​

Supply chain continuity of selected components should be checked. Priority should be given not only to parts available in stock but to components in "Active" status by manufacturer. Additionally, defining alternative MPN (Manufacturer Part Number) for critical parts is one of best practices for production continuity. This check prevents production pauses caused by supply shortages.

58. Is RoHS compliance verified?​

All components being compliant with RoHS (Restriction of Hazardous Substances) regulation is important both for legal requirement and environmental responsibility. Components without lead, cadmium, mercury, hexavalent chromium and specified brominated compounds should be preferred. Compliance information is generally clearly stated in manufacturer data sheets or supplier portals; these documents should be verified before production.

Connectors and Harness​

59. Are harness pinout and specifications defined?​

For all cable harnesses between board and external system, pin arrangement (pinout), wire colors, cross-section (AWG) values and cable type should be clearly defined. This information should be in both mechanical drawings and schematic notes. Proper documentation eliminates incorrect connection risk during production and increases test-jig compatibility. Additionally, cable lengths and connector directions should be predetermined for system integrity.

60. Are board edge connectors verified?​

Board edge mounted connectors (for example edge connector, mezzanine, flat flex etc.) PCB thickness, pin alignment, assembly direction and mechanical endurance should be checked according to manufacturer datasheet. Incorrectly selected board edge connector can lead to both contact problems and mechanical strain. Therefore, physical fit tests must be done before prototype.

61. Are connector fixing / shielding pins determined?​

Status of mechanical fixing pins and shielding connections if any of connectors should be clearly defined. In some connectors, these pins are connected to GND while in others they should be left isolated. Correct decision plays determining role in terms of EMI performance and mechanical robustness. Clear marking of these connections on schematic prevents confusion in PCB design.

Documentation and Outputs​

62. Are table of contents, legend and headings ready?​

All schematic pages should be completed with table of contents (index), symbol legend and section headings to support project integrity. These elements provide quick orientation especially for new team members and external auditors in multi-page projects. Symbols, abbreviations and signs used in legend should be explained; version, date and designer information should be in title blocks.

63. Are critical signals named?​

Critical nets such as power, clock, reset, communication or error signal should be named clearly and descriptively. Instead of ambiguous names like "NET1" or "SIG_A", functional names like +3V3_EN, SYS_RST_N, CLK_8M should be preferred. This practice facilitates both intra-team communication and debugging processes.

64. Is PDF export taken?​

Final state of design should be saved as PDF output containing revision number and timestamp. This document has official reference quality in production, review and archiving processes. Links (for example "off-page" references) and metadata in PDF file should be preserved. Additionally, file naming standard (e.g., ProjectName_SCH_R1.2.pdf) should be determined.

65. Are test points (TP) marked?​

Points to be accessed in all measurement, debug and quality control stages should be defined with TP (Test Point) label. Each test point should be labeled with its function or measurement type (e.g., TP_VCC, TP_UART_TX). This practice saves time in post-production test processes and facilitates service maintenance.

66. Are software / hardware notes added?​

Hardware's interaction points with software should be clearly stated on schematic. For example, connections like "GPIO23 → LED_STATUS", "ADC1_CH4 → TEMP_SENSOR" or "BOOT_SEL → DIP1" should be added as notes. This information creates vital reference for firmware developers and prevents incorrect pin matching.

67. Is EP pad connection specified?​

Connection type (GND, AGND, PAD_ISOLATED etc.) of integrated circuits containing thermal pad or exposed pad (EP) should be clearly specified on schematic. Incorrect connection directly affects thermal performance and EMC characteristic. This information should also be clearly marked in PCB layer plan.

68. Is pin list reported?​

Pin function report of multi-pin components such as microcontroller, FPGA or connector should be created. This report is basic document for both software team and hardware test team. It is recommended to automatically generate using CAD tools' "netlist" or "pin report" features.

69. Are passive values properly written?​

All resistor, capacitor and inductance values should be written in accordance with engineering unit standard: 10kΩ, 100nF, 4.7µH etc. Working with full units instead of ambiguous or abbreviated values (.1u, 100n) reduces error risk in production and quality control processes.

70. Are generic parts explained visually?​

Generic or non-manufacturer-specific parts (for example "HEADER_10PIN", "LED_RED", "SW_PUSH") should be visually explained or example reference part should be specified. This prevents incorrect component selection in supply and prototype production. Additionally, example manufacturer number (MPN) or 3D model link corresponding to each generic part used in project should be added to document.

Environmental and Worst Case Reviews​

71. Are worst temperature conditions checked?​

All components of design should be evaluated and verified at worst-case scenario within system's target operating temperature range. In industrial, automotive or outdoor applications, this range generally varies between –40°C to +85°C (even +125°C). "Operating Temperature Range" value in each component's datasheet should meet project requirements. Additionally, voltage deviations that may occur with effect of temperature increase and thermal equilibrium times should be considered.

72. Are capacitor temperature / voltage drops evaluated?​

In ceramic capacitors, especially in dielectric types like X5R/X7R, it should not be forgotten that nominal capacitance value can drop significantly under voltage and temperature. For example, 6.3 V nominal capacitor can lose 40% of its capacitance while working under 5 V. Therefore, de-rating should be applied and operating voltage should be kept around 50–60% of nominal maximum. This check is critical for stability especially in power lines and timing circuits.

73. Are tantalum capacitance sudden discharge risks reviewed?​

Tantalum capacitors offer high energy density but are sensitive to sudden charge/discharge conditions. Therefore, measures such as series resistance, current limitation or soft-start should be considered before using on supply lines. Misuse can cause permanent failure or explosion of capacitor. Alternatively, polymer capacitors can be preferred in systems requiring high safety.

74. Is BJT reverse BE current risk analyzed?​

In bipolar transistors (BJT), base-emitter (BE) voltage applied in reverse direction can damage transistor structure especially in fast switched circuits. In this case, series resistance or protection diode for reverse direction current limitation should generally be added. This detail should not be overlooked especially in low voltage signal circuits or op-amp output drivers.

75. Are FET / logic level protections evaluated?​

MOSFET and logic level lines should be protected against both overvoltage pulses (transient spikes) and ESD effects. Protection elements such as zener, TVS diode or RC snubber should be evaluated for gate pins. Additionally, digital inputs working at logic levels should be supported with series resistance or protection diode against voltage deviations that may come from external lines. These measures are basic factors determining system's long-term reliability.

Additional Practices​

76. Are 0Ω bridges added to risky lines?​

Adding 0Ω resistor (jumper) to lines with high probability of modification in later stages of design or carrying error risk enables modification without requiring major revision. These elements can also be used as current measurement point, noise isolation or configuration selector. Defining these flexibility points at early stage provides great advantage in prototype and test processes.

77. Are line types separated by colors?​

Signal types (for example power, analog, digital, communication, control) should be visually separated with different colors or line styles on schematic. This practice both increases readability and enables easy distinction of line types during error review. Especially in large projects or teamwork, visual standardization saves significant time.

78. Are critical component descriptions added?​

Short note descriptions should be added for components with complex function or sensitive behavior. For example, descriptions like "This LDO provides MCU's analog supply – low noise type should be selected" prevent information loss in subsequent design revisions. Additionally, it helps even non-engineer teams in production or maintenance processes to correctly understand component functions.

79. Are chip current draws annotated?​

Average and maximum current consumption should be specified on schematic or in note section for each major integrated circuit (for example MCU, FPGA, RF transceiver). This information is of great importance for power supply capacity verification, thermal analysis and test planning. Additionally, it provides direct reference when creating system's total current budget.

80. Is revision summary and change log up to date?​

Every change made in project file should be documented under revision log. In this record, date, person making change, scope and reason of change should be clearly written. Together with version control systems (for example Git), this record ensures traceability and strengthens team coordination.

81. Are stack-up and impedance targets specified in schematic notes?​

Before PCB production, layer structure (stack-up), impedance targets, trace widths and dielectric thicknesses should be specified in schematic notes. This information prevents confusion in technical communication with manufacturer. For example: clear values like "50 Ω single-ended, 100 Ω differential, 1.6 mm FR-4, 4-layer stack-up" guarantee production accuracy.

82. Is clean and dirty GND separation defined in sensitive ADC / DAC lines?​

To preserve analog measurement accuracy, AGND (analog ground) and DGND (digital ground) separation should be made, these points should only be combined at single reference point (star ground). This separation prevents digital noise from mixing into analog signals in ADC and DAC lines. Additionally, this separation should be maintained in power and signal routing plans.

83. Is power-up sequencing diagram added?​

In systems with multiple supply lines, opening order (power-up sequence) of lines should be specified as diagram or note on schematic. This information is vitally important both in hardware tests and firmware initialization routine planning. For example: clear sequence definition like "3V3 → 1V8 → 1V2, with 10 ms intervals" should be made.

84. Are power line filter and ferrite bead values verified according to datasheet?​

Ferrite bead and RC filter components should be selected according to manufacturer recommendations of used integrated circuits. Ferrite with incorrect impedance or frequency characteristic can cause resonance instead of suppressing noise. Therefore, ferrite selection should be made suitable for frequency range and current capacity specified in datasheet.

85. Are test / calibration pins reported labeled to software team?​

All test, calibration or debug pins (for example SWD, UART_DBG, ADC_CAL_IN) should be shared with software team in labeled form. This information is necessary for error-free progress of firmware development and test processes. Additionally, function and availability of pins should be listed in project documentation.

86. Are EMC measures (RC snubber, ferrit bead) shown on schematic in critical lines?​

All passive filtering elements (RC snubber, ferrite bead, common-mode choke etc.) used for electromagnetic compatibility (EMC) should be visible on schematic. These elements are necessary especially for fast switched power lines, motor drivers and clock signals. Position and value of filter circuits should be specified as note to prevent confusion during production or in revisions.